a. Field of the Invention
The present invention generally relates to semiconductor manufacturing, and more particularly to focal plane determination in lithographic processes.
b. Background of Invention
As semiconductor groundrules shrink, efforts may be made to enable the use of current generation lithography tools (e.g., high NA 193 nm immersion) for technology nodes below, for example, 20 nm or 22 nm. These efforts may, among other things, be a function of the need to reduce lithography costs and manufacturing delays associated with advancing new lithography tools.
One factor that may contribute to limiting the capabilities of advanced lithography tools is depth of focus. There are various factors which contribute to focus variability when a wafer is being exposed during a lithographic process. A significant factor associated with the advent of focus variability is the field wafer topography. For example, back-end-of-the-line (BEOL) copper (Cu) chemical mechanical polishing (CMP) processes may contribute to generating surface topography variations on each metal layer within a reticle field (e.g., exposure area of a wafer or chip).
A surface topography variation on a BEOL metal layer within the reticle field may depend on geometric design parameters such as, for example, local metal pattern densities, electrical connection linewidths, and shape perimeter densities at both the level of the CMP and at underlying metal levels. In other words, the CMP process applied to the BEOL metal layer may create a 3-dimensional (3D) topography on the metal layer rather than a planar surface. Moreover, as new metal layers are fabricated and polished using CMP, the 3D topography of the underlying metal layers also contributes to the topography variations of each new fabricated layer.